TVC development has proceeded based on the abstraction that a video card is composed of four components. These components are: #1 a large block of memory used for the frame buffer, depth buffer, textures, commands, etc., #2 a display module that pushes pixel values to an external display, #3 a communications link to a host processor and #4, a block of drawing functional units driven by the host that perform drawing operations by reading and writing to the large block of memory.
Most of the complexity specific to a video card is in the block of functional units. The functional units may be developed largely independently of each other and of the implementation of the other components; provided all components are designed around a common internal interconnect.
TVC development thus far has been done on a Digilent D2E development kit based around a Xilinx Spartan XC2S200E FPGA. See a picture here. The memory for the frame buffer is an old 8MB 72 pin simm hardwired to a wire wrap expansion board. The display module consists of VGA signals generated by a resistor network on a Digilent DIO2 peripheral board. The communications link is the EPP port provided by the D2E board. The functional units (and the overall design) have been coded in VHDL.
The current development hardware has been useful in that it was inexpensive enough to encourage experimentation and flexible enough to allow a successful implementation. Unfortunately the resistor network only allows 256 colors, the EPP port only allows about 1 MB/sec of command bandwidth and the 72 pin simm only provides about 50 MB/sec of memory bandwidth. All of these constraints even individually are quite crippling, but all can be expanded by a transition to a new development platform, (though this original implementation has served quite well).
Eventually a move to a pci-e development kit will be made. Because an open pci express core apparently does not exist, a pcb header will be made to quick-n-dirty add an EPP port to the development kit. The EPP port will allow immediate resumption of development using the current driver software and it is expected that the EPP communications link will serve as a tool to greatly ease the implementation of a PCI express core. The move to a new development platform (even without a functional pci-e connection) will remove the constraint of a low bit display and will greatly increase the memory bandwidth.
